This invention relates to apparatus and methods for debugging integrated circuits. More particularly, this invention pertains to apparatus and methods for monitoring dynamic or static internal signals in an integrated circuit.
Rapid advances in integrated circuit technology have enabled more and more electronic circuit elements to be implemented in smaller and smaller integrated circuit devices. As circuit density has increased, the functional complexity of integrated circuit devices has also increased. As a result, many products that include integrated circuits have become smaller, lighter, quieter, more powerful and more energy efficient. The trend toward increased integrated circuit functionality and decreased device size seems likely to continue for the foreseeable future. As integrated circuits have become more complex, however, the ability to test and debug integrated circuits has become more difficult. Further, conventional techniques for testing integrated circuits generally do not permit continuous monitoring of internal signals, such as in internal state machines, counters, flow control signals, data at various stages in the pipeline and any other dynamic or static signals of interest whose continuous observability could significantly simplify circuit debugging.
A common technique for testing and debugging integrated circuits is described with reference to FIG. 1. Integrated circuit 10a includes circuit blocks A, B, C, D and E, each of which may include large numbers of electronic circuit elements and signals. For testing and debugging purposes, it may be desirable to monitor internal signals in each circuit block. For example, it may be desirable to monitor internal signals A1-A3, B1-B2, C1-C3, D1-D2 and E1 in circuit blocks A, B, C, D and E, respectively. To accomplish this goal, internal signals A1-A3, B1-B2, C1-C3, D1-D2 and E1 may be connected to external pins 12a-12k, respectively.
One problem with this previously known internal signal monitoring technique, however, is that it is not easily scalable. Indeed, to monitor three additional internal signals in integrated circuit 10, three additional external pins are required. Because an integrated circuit package can support only a limited number of external pins, the number of internal signals that may be routed to external pins often cannot be easily increased.
One previously known technique for solving the problem of limited external pin count is described with reference to FIG. 2. Integrated circuit 10b includes multiplexer (“MUX”) 14, which has input nodes coupled to internal signals A1-A3, B1-B2, C1-C3, D1-D2 and E1, a control input node coupled to control signal SELECT, and an output node coupled to external pin 16. MUX 14 functions like a controllable switch, coupling one of internal signals A1-A3, B1-B2, C1-C3, D1-D2 and E1 to external pin 16 based on the value of control signal SELECT. Thus, if control signal SELECT is a four-bit signal, up to sixteen internal signals may be selectively coupled to external pin 16 via MUX 14. To route additional internal signals from circuit 10b to external pin 16, additional input nodes may be added to MUX 14, and the bit size of control signal SELECT may be increased. Alternatively, if another external pin is available, the additional internal signals may be routed to a second MUX, which may be controlled using a second multi-bit control signal.
There are several problems, however, with this previously known internal signal monitoring technique. First, circuit 10b may be susceptible to increased noise and crosstalk issues. Indeed, because internal signals A1-A3, B1-B2, C1-C3, D1-D2 and E1 may need to be routed over relatively long distances to MUX 14, the internal signals may interfere with the operation of circuitry adjacent to the long signal traces. Although various layout techniques may be used to minimize the effect of such noise and crosstalk, such techniques typically consume valuable real estate and increase the size of the integrated circuit device.
In addition, the technique illustrated in FIG. 2 is inefficient in terms of size and power consumption, particularly as the number of monitored signals increases. Indeed, as more internal signals are monitored, the amount of space required to route the various signals to MUX 14, and the size of the MUX itself, becomes prohibitively large. Further, because the monitored signals typically toggle at a very high clock rate, the power required to drive these simultaneously active signals over long signal traces from the internal circuit nodes to MUX 14 becomes unacceptably high.
Moreover, the technique in FIG. 2 is not practically scalable. Indeed, when an internal signal trace is added to a circuit block, the trace often must be routed through numerous other circuit blocks on the integrated circuit. Because the various circuit blocks may be designed by multiple engineers, the addition by one engineer of the single internal signal trace may need to be communicated to all the engineers who worked on the integrated circuit, and may impact all of other circuit blocks. As a result, the technique shown in FIG. 2 is not practical.
In view of the foregoing, it would be desirable to provide improved methods and apparatus for monitoring internal signals in integrated circuits.
It further would be desirable to provide lower noise methods and apparatus for monitoring internal signals in integrated circuits.
It additionally would be desirable to provide scalable methods and apparatus for monitoring internal signals in integrated circuits.
It also would be desirable to provide area-efficient methods and apparatus for monitoring internal signals in integrated circuits.
It moreover would be desirable to provide power-efficient methods and apparatus for monitoring internal signals in integrated circuits.